1. Field of the Invention
The present invention relates to an image signal recording and reproducing system for recording an image signal on a recording medium and for reproducing the image signal recorded on the recording medium.
2. Description of the Related Art
Still video (SV) systems are known as one type of apparatus for recording and reproducing still image signals. The SV systems are arranged to record TV signals based on the current television signal format on 2-inch magnetic discs by utilizing frequency modulation. However, the resolution attained with such a system is limited by that of the current TV system. For this reason, it is pointed out that, if a printer is used to produce a printout as the final output from a still image recorded by such an SV system, the obtained image quality (particularly, the resolution) will be low compared to that of a typical silver-halide photograph.
It is also known that several novel television systems such as a high-definition television (HDTV) system have recently been proposed. The HDTV system is characterized by about one thousand scanning lines which have about twice the number of scanning lines used in the current HTSC system, and is also provided with a corresponding horizontal signal band. Accordingly, it has been strongly desired to develop a still image recording and reproducing system capable of recording and reproducing a still image signal which compares with the image quality of 1,000.times.1,000 pixels (per square image area on a TV screen) realized by the HDTV system or the like.
In light of such a situation, the SV systems adopt high-band (wide-band) recording formats to effect recording and reproduction on and from recording media.
However, it is desired that an improvement in the image quality of the SV systems be achieved while compatibility with the conventional format is being maintained.
One method of improving the image quality while maintaining compatibility with the conventional format is the CHSV (compatible high definition SV) system which was proposed by the applicant of the present invention.
The following is an explanation of the CHSV system proposed by the present applicant.
The CHSV system utilizes an art called analog transfer of sampled values.
A system for analog transfer of sampled values is, as shown in FIG. 1, characterized by transfer-path characteristics (LPF characteristics) and re-sampling. More specifically, the system is arranged to pass the input sampled value through a frequency-modulation section, an electromagnetic conversion section and a frequency-demodulation section and then to restore the sampled value by re-sampling.
The principle of the analog transfer of sampled values is explained in more detail with reference to FIGS. 2(a) to 2(f). In the following explanation, it is assumed that a sequence of sampled values of period T, shown in FIG. 2(a), is recorded and reproduced. The transfer path shown in FIG. 1, which includes the frequency modulation section, the electromagnetic conversion section and the frequency demodulation section, has a low-band transmission characteristic, i.e., a low-pass filter (LPF) characteristic. FIG. 2(b) shows the output of this transfer path. The illustrated transfer-path output is re-sampled with a sequence of re-sampling pulses of period T and in correct phase, such as that shown in FIG. 2(c), to provide the signal shown in FIG. 2(d). As can be seen from FIG. 2(d), the sequence of input sampled values is correctly reproduced (transferred). However, if the re-sampling pulses are out of phase as shown in FIG. 2(e), the sequence of sampled values is not correctly reproduced (transferred), resulting in ringing such as that shown in FIG. 2(f). Accordingly, to accomplish the above analog transfer of sampled values, during reproduction (on the receiving side) it is necessary to generate a sequence of re-sampling pulses of correct frequency (period), corresponding to the reproduced (received) sampled-value signals, and it is also necessary that a sequence of re-sampling pulses of correct phase corresponding to the reproduced (received) sampled-value signals be generated. The other requirement for completely transferring sampled-value signals is as follows: the transfer path, including the frequency modulation and demodulation sections and the electromagnetic conversion section, has a linear phase and a frequency characteristic which exhibits symmetrical roll-off centered at a sampling frequency f.sub.s (=1/2T).
More specifically, it is necessary that the transfer path have an LPF characteristic such as that shown in FIG. 3. The outline of the analog transfer of sampled values has been explained.
The following is an explanation of a method of recording the chrominance (Y) signal on the basis of the CHSV system.
FIG. 4 is a diagram showing sample points for a Y signal to be recorded on a magnetic disc. As shown in FIG. 4, the sample points for the Y signal are arranged in offset form for the purpose of subsampling transfer. Also, 650 (1300/2) sample points are in a row and 500(1000/2) sample points are in a column. The sampled values contained in rows A.sub.1, A.sub.2, . . . are recorded on a single track on the magnetic disc, the sampled values contained in rows B.sub.1, B.sub.2, . . . on another track, and so on. In this manner, the signals indicating all the sample points are recorded on a total of four tracks.
The sample points are recorded on each track in a format according to a known SV format. FIG. 5 shows the frequency allocation of a signal recorded in the SV format. As shown in FIG. 5, in the SV format, the basebands of recorded Y and C signals are 7 MHz or less and 1 MHz or less, respectively.
In FIG. 4, each row includes 650 Y-signal sample points, and these points are recorded within the horizontal effective frame period (53 .mu.sec or less) of a NTSC-TV signal. Accordingly, the corresponding sampling frequency f.sub.s (refer to FIG. 3) is 6.1 MHz or less. In the above-described manner, the Y signal having a band such as that shown in FIG. 3 is recorded.
FIGS. 6(a) and 6(b) show two different recording patterns formed on the magnetic disc on the basis of the CHSV system. FIG. 6(a) shows the recording pattern formed when a 2-channel (2-ch) head is utilized, while FIG. 6(b) shows the recording pattern formed when a 4-channel (4-ch) head is utilized. (Needless to say, the 4-ch head can be utilized to form either of the recording patterns shown in FIGS. 6(a) and 6(b).)
The recording pattern of FIG. 6(a) is formed as follows. First, the sampled values of the Y signal on the row A.sub.i and the row B.sub.i (i=a positive integer), i.e., the sampled values for two channels, are simultaneously recorded on the first and second tracks, respectively, by means of the 2-ch head. Then, the 2-ch head is moved to the third and fourth tracks (this movement is not needed when a 4-ch head is in use), and the sampled values of the Y signals on the row D.sub.i and the row C.sub.i, i.e., the sampled values for two channels, are simultaneously recorded. During this time, as illustrated, in order to maintain compatibility with the conventional SV format, the positional relationship between the tracks for recording the sampled values of the Y signal on the rows D.sub.i and C.sub.i are reversed.
In general, simultaneous 2-ch recording involves the problem of crosstalk arising between signals in a head during recording. However, the use of the recording method described above makes it possible to solve such problem since well-known H alignment is effected between two heads during simultaneous recording.
Where a 4-ch head is utilized, recording may be performed in accordance with the recording pattern shown in FIG. 6(b). More specifically, the sampled values of the Y signal on the row A.sub.i and the row B.sub.i, i.e., the sampled values for two channels, are simultaneously recorded on the first and third tracks, respectively. Then, the sampled values of the Y signals on the row C.sub.i and the row D.sub.i, i.e., the sampled values for two channels, are simultaneously recorded on the second and fourth tracks, respectively.
With the above-described recording method, in the case of the recording pattern of FIG. 6(a), it is possible to reproduce a frame image based on the conventional SV format from the second and third tracks. As for the recording pattern of FIG. 6(b), it is possible to reproduce a frame image based on the conventional SV format from the first and second tracks or the third and fourth tracks.
The process of recording a Y signal in the CHSV system is as described above.
The following is an explanation of the process of recording the color-difference line-sequential (C) signal in the CHSV system.
FIGS. 7(a), 7(b) and 7(c) show the relationship between the recording sample patterns of a Y signal, a C.sub.R (R-Y) signal and a C.sub.B (B-Y) signal. In the conventional SV format, a recording band allocated for a color-difference signal is about 1/6 that of the Y signal, and the color-difference signal is recorded in a line-sequential manner. Accordingly, the sample patterns of the color-difference signals C.sub.R and C.sub.B in the CHSV system are as shown in FIGS. 7(b) and 7(c), respectively. In the right-hand side of each of FIGS. 7(b) and 7(c), lines of Y signals to be recorded on individual tracks are indicated by reference numerals A.sub.i, B.sub.i, C.sub.i and D.sub.i, respectively. Although the lines of the Y signals do not completely coincide with the lines of the corresponding C signals, this patterns is intended for compatibility with the SV format.
FIG. 8 is a table which shows the relationship between the recording positions of the Y and C signals. In the table, "First Step" indicates "simultaneous 2-ch recording executed in a first step", and "Second Step" likewise indicates "simultaneous 2-ch recording executed in a second step". As described above, in the first step, recording for tracks 1 and 2 is executed and, in the second step, recording for tracks 3 and 4 is executed. Referring to FIG. 8, for example, in the first step, Y(A.sub.i) and C.sub.R (A.sub.i)/C.sub.B (A.sub.i) are recorded on the first rack. Y(A.sub.i) indicates a Y signal consisting of a sequence of Y sampled values along the line A.sub.i shown in FIG. 7(a) and C.sub.R (A /C.sub.B (A.sub.i) indicates a color-difference line-sequential signal which is formed by a C.sub.R signal consisting of a sequence of C.sub.R sampled values along the line A.sub.i shown in FIG. 7(b) and a C.sub.B signal consisting of a sequence of C.sub.B sampled values along the line B.sub.i shown in FIG. 7(c). C.sub.R (A.sub.i)/C.sub.B (A.sub.i) starts with a C.sub.R signal. In FIG. 8, imaging-section outputs Y.sub.1, Y.sub.2, R, B are signals which are simultaneously output from the imaging section of a CHSV camera, which will be described later.
The following is an explanation of the construction of the CHSV camera (a device constituted by an imaging section and a recording section).
The CHSV camera shown in FIG. 9 is, as described above, arranged to record image signals for one picture by continuously performing simultaneous 2-ch recording twice. In the first step shown in FIG. 8, the following process is performed. Y and C signals are input to each of SV recording processing circuits 826 and 827. Each of these circuits 826 and 827 effects predetermined processes such as emphasis, frequency modulation and the like on the input Y and C signals, then frequency-multiplexes the Y and C signals thus processed, and then outputs the frequency-multiplexed signal. Adders 828 and 829 add sine-wave signals, as reference signal for TBC (time base correction) in reproduction, to the output signals from the corresponding SV recording processing circuits 826 and 827 (The frequency of the sine-wave signal is 2.5 MHz or near (2.5 MHz corresponds to the gap between FM-Y and FM-C as shown in FIG. 5)). The signals output from the adders 828 and 829 are amplified by recording amplifiers 830 and 831, respectively. The resulting signals for two channels are simultaneously recorded on predetermined tracks of a magnetic disc 834 by 2-ch heads 832 and 833, respectively. In the second step, after the 2-ch heads 832 and 833 have been moved, recording is performed in a manner similar to that explained in the above first step.
The imaging section 801 shown in FIG. 9 is explained below.
FIG. 10 is a partial schematic view showing the construction of a color filter assembly for use with a single solid-state image sensor which constitutes the imaging section 801. As shown in FIG. 10, the color filter assembly consists of Y (chrominance) filters which are arranged in checkered form and the remaining R and B filters which are arranged in line-sequential form.
FIG. 11 is a view showing an example of the construction of the imaging section 801 which includes a solid-state imaging device provided with the color filter assembly shown in FIG. 10.
Referring to FIG. 11, the imaging section 801 includes a solid-state image sensor 1301 having the color filter assembly shown in FIG. 10 and sample-and-hold circuits 1302 to 1305. The solid-state image sensor 1301 has pixels of the order of 1300 pixels.times.1000 pixels and an arrangement capable of simultaneously reading out signals for two adjacent horizontal lines every other two lines.
In FIG. 11, of the simultaneously read signals for two lines, the Y signal (Y.sub.1) of the upper line is output to a signal line 0-1, the Y signal (Y.sub.2) of the lower line to a signal line 0-3, an R signal to a signal line 0-2, and a B signal to a signal line 0-4.
The sample-and-hold circuits 1302 to 1305 sample, hold and output the Y signal (Y.sub.1), the Y signal (Y.sub.2), the R signal and the B signal at predetermined timings, respectively.
FIG. 12 is a schematic view showing a specific example of a solid-state image sensor having the aforesaid arrangement capable of simultaneously reading out signals for two adjacent horizontal lines every other two lines, and the illustrated solid-state image sensor is made from a MOS type solid-state image sensor.
The MOS type solid-state image sensor of FIG. 12 is of a TSL (transversal signal line) type which is well known.
Since, even in the CHSV system, the MOS type solid-state image sensor shown in FIG. 12 allows signals to be read in horizontal order, it is possible to provide the effect of suppressing smear or the like.
Furthermore, since the signal-reading operation of the MOS type solid-state image sensor is based on an X-Y address method, it is possible to simultaneously read two lines of signals as described above. For the sake of simplicity, no detailed description is given of such a signal-reading operation.
The following is an explanation, referring to FIG. 9, of the signal processing in which the imaging section 801 is driven to output the Y.sub.1, Y.sub.2, R and B signals by an imaging-section driving circuit 808 in synchronism with a synchronizing signal output from a clock generator 813, and those signals are input to the SV recording processing circuits 826 and 827. The signal processing operations associated with Y and C signals are separately explained in that order.
To begin with, a signal processing operation for the Y signal is explained. The Y.sub.1 and Y.sub.2 signals output from the imaging section 801 (refer to FIG. 8 for the details of Y.sub.1 and Y.sub.2) are supplied to adders 814 and 816, respectively. The adders 814 and 816 add, to the respective Y.sub.1 and Y.sub.2 signals, phase reference signals output from a phase reference signal generator 818. Such phase reference signal provides a phase reference for re-sampling operation during reproduction, as will be explained later. One phase reference signal may be inserted every 1H period (horizontal synchronizing period) or every 1V period (vertical synchronizing period). FIG. 13 shows an example in which one phase reference signal is inserted during every 1H period. As shown in FIG. 13, the phase reference signal is a three-level signal, and R indicates a phase reference point.
The Y.sub.1 and Y.sub.2 signals, to which such phase reference signals have been added by the respective adders 814 and 816, are respectively passed through low-pass filters (LPFs) 802 and 805 each of which transmits a frequency band of 6 MHz. The signals output from the LPFs 802 and 805 are passed through gamma correction circuits (.gamma..sub.Y) 821 and 823 and input to the SV recording processing circuits 826 and 827, respectively.
.gamma..sub.Y 's 821 and 823 serve as .gamma. correction circuits for the corresponding transfer paths and are inserted for the purposes of improving the S/N ratio of a dark portion of a chrominance signal, maintaining compatibility with the conventional SV format, and so on.
Then, the signal processing operation for the C signal is explained. The R and B signals output from the imaging section 801 (refer to FIG. 8 for the details of R and B) are respectively passed through LPFs 804 and 807, each of which transmits a frequency band of 1 MHz, and are input to switch circuits S.sub.1 and S.sub.2. The switch circuits S.sub.1 and S.sub.2 operate to switch every 1H period, thereby providing color line-sequential signals R/B (output from S.sub.1) and B/R (output from S.sub.2).
A subtracter 809 subtracts the signal Y.sub.1 output from LPF 803 having a transmission frequency band of 1 MHz from the output signal from the switch circuit S.sub.1, while a subtracter 810 subtracts the signal Y.sub.2 output from LPF 806 having a transmission frequency band of 1 MHz from the output signal from the switch circuit S.sub.2. A color-difference line-sequential signal C.sub.R /C.sub.B is output from the subtracter 809 and a color-difference line-sequential signal C.sub.B /C.sub.R from the subtracter 810.
The color-difference line-sequential signal C.sub.R /C.sub.B and the color-difference line-sequential signal C.sub.B /C.sub.R are sampled by respective sample-and-hold circuits 811 and 812, thereby providing the sample patterns C.sub.R and C.sub.B shown in FIGS. 7(b) and 7(c). The sampled signals are supplied to adders 815 and 817, respectively. Sampling clocks are supplied from the clock generator 813.
In the respective adders 815 and 817, phase reference signals are added to the sampled signals as in the case of the Y signal. (However, a phase reference point for the C signal does not have to coincide with the phase reference position for the Y signal.)
The signals output from the adders 815 and 817 are input to the SV recording processing circuits 826 and 827 through LPFs 819 and 820 and gamma correction circuits (.gamma.c) 822 and 824, respectively.
The following is an explanation of the construction of a CHSV reproducing apparatus.
FIG. 14 is a block diagram showing the construction of the CHSV reproducing apparatus.
The signal reproduced from a magnetic disc 1501 by a magnetic head 1502 is input to both an SV reproduction processing circuit 1504 and a BPF 1505 through a preamplifier 1503.
The SV reproduction processing circuit 1504 performs frequency-separation of FM-Y and FM-C signals (refer to FIG. 5) from the input reproduced signal, then applies frequency demodulation, de-emphasis and the like to each of the signals, and then outputs a reproduced Y signal and a reproduced C signal.
Reverse gamma correction circuits (.gamma..sub.Y.sup.-1) 1506 and (.gamma..sub.c.sup.-1) 1507, which follow the SV reproduction processing circuit 1504, are provided for recovering the original signal from signals which were subjected to transfer-path .gamma..sub.Y and .gamma..sub.C correction during recording, respectively. The Y signal is corrected by the reverse gamma correction circuits (.gamma..sub.Y.sup.-1) 1506, passed through an LPF 1508, and input to an A/D converter 15d13, while the C signal is corrected by the reverse gamma correction circuits (.gamma..sub.c.sup.-1) 1506, passed through an LPF 1509, and input to a variable delay circuit 1528.
The following is an explanation of a process for generating re-sampling clocks during reproduction.
Referring to FIG. 14, the BPF 1505 separates a reference signal f.sub.r for reproduction TBC from a reproduced signal. The reference signal f.sub.r is input to a PLL (Phase-Locked Loop) circuit 1526. The PLL circuit 1526 generates and outputs a clock f.sub.so which is phase-synchronized with the signal f.sub.r and which has a frequency equal to the frequency of a re-sampling clock for a Y signal.
A phase control circuit 1511 for a Y-signal re-sampling clock executes phase control of the re-sampling clock f.sub.so thus obtained, thereby outputting a Y-signal re-sampling clock f.sub.s1, the phase of which has, as shown in FIG. 15, a predetermined relationship to the phase reference point of the aforesaid Y-signal re-sampling phase reference signal added to the reproduced Y signal.
A clock (f.sub.s1 /6) is used as a re-sampling clock for a C signal. The clock (f.sub.s1 /6) is obtained by dividing the aforesaid clock f.sub.s1 by six by a 1/6 frequency divider 1527. The 1/6 frequency divider 1527 consists of elements such as a counter, and the count of the counter is reset by the falling edge of a synchronizing signal. The C signal output from the LPF 1509 is delay-controlled by the variable delay circuit 1528 whose delay time is controlled by a C-signal delay control signal generating circuit 1529, whereby the phase relationship between the C-signal re-sampling clock (f.sub.s1 /6) and the re-sampling phase reference point added to the C signal is rendered constant. The C signal thus processed is supplied to an A/D converter 1514.
The following is a detailed explanation of the construction of each of the PLL circuit 1526, the phase control circuit 1511 for a Y-signal re-sampling clock and the C-signal delay control signal generating circuit 1529.
FIG. 16 is a block diagram showing the construction of the PLL circuit 1526.
In a phase comparator 1601, the input reference signal f.sub.r for reproduction TBC is phase-compared with a signal obtained by dividing the clock output from a voltage controlled oscillator (VCO) 1604 by N in a 1/N frequency divider 1603. A band-pass filter (BPF) 1608 is provided for extracting the basic (sine-wave) component of the clock output from the 1/N frequency divider 1603. The clock output from VCO 1604 is divided by M by a 1/M frequency divider 1605 and output as the clock f.sub.so.
It is assumed here that the frequency relationship f.sub.r =(M/N)f.sub.s1 is established between the re-sampling clock f.sub.s1 and the TBC reference signal f.sub.r.
FIG. 17 is a block diagram showing the construction of the Y-signal re-sampling clock phase control circuit 1511.
In this phase control circuit 1511, the clock f.sub.so obtained in the PLL circuit 1526 is passed through a variable delay circuit 1705, and the variable delay circuit 1705 is controlled so that the Y-signal re-sampling clock f.sub.s1 bears a constant relationship with the phase reference point of the re-sampling phase reference signal added to the reproduced Y signal.
A control signal for the variable delay circuit 1705 is generated by a Y-signal re-sampling clock phase control signal generating circuit 1706 which is surrounded by dashed lines in FIG. 17.
The illustrated circuit 1706 includes a counter circuit 1707 which operates in response to the re-sampling clock f.sub.s1. The counter circuit 1707 utilizes a synchronizing (SYNC) signal as a reset signal. As shown in FIG. 18, the counter circuit 1707 counts the clock f.sub.s1 by utilizing the falling edge of the horizontal synchronizing signal as a reference point, and outputs pulses G1 and G2 at the timing shown in FIG. 18. The circuit 1706 also includes sample-and-hold circuits 1703 and 1704 for sampling and holding Y signals at the timings of the pulses G1 and G2, respectively.
A differential amplifier 1702 obtains the difference between the outputs from the sample-and-hold circuits 1703 and 1704. The obtained difference signal is passed through a low-pass filter (LPF) 1701 which serves as a loop filter. The signal passed through LPF 1701 is output as a phase control signal to control the delay time of the variable delay circuit 1705.
The variable delay circuit 1705 provides correct phase control in the above-described manner, whereby the re-sampling clock is output at the timing shown in part f.sub.s1* of FIG. 18.
The variable delay circuit 1705 may consist of, for example, a circuit in which a plurality of CMOS buffers of the type shown in FIG. 19 are connected and in which a source voltage V.sub.DD is controlled to vary the delay time.
FIG. 20 is a block diagram showing the construction of the C-signal delay control signal generating circuit 1529 shown in FIG. 14.
The circuit shown in FIG. 20 includes a counter circuit 2005 arranged to operate in response to the clock f.sub.s1 /6 output from 1/6 frequency divider 1527 of FIG. 14. The counter circuit 2005 utilizes the synchronizing (SYNC) signal as a reset signal. As shown in FIG. 21, the counter circuit 2005 counts the clock f.sub.s1 /6 by utilizing the falling edge of the horizontal synchronizing signal as a reference point, and outputs the pulses G1 and G2 at the timing shown in FIG. 21.
The circuit 1706 also includes sample-and-hold circuits 2003 and 2004 for sampling and holding C signals at the timings of the pulses G1 and G2, respectively.
A differential amplifier 2002 outputs the difference between the output from the sample-and-hold circuits 2003 and 2004. The obtained difference signal is passed through a low-pass filter (LPF) 2001 which serves as a loop filter. The signal passed through LPF 2001 is output as a C-signal delay control signal.
Part C* of FIG. 21 shows the C signal which is correctly delay-controlled.
A CCD delay circuit or the like may be used as the C-signal variable delay circuit 1528 shown in FIG. 14.
The method of generating re-sampling clocks in reproduction is as described above.
The respective A/D converters 1513 and 1514 of FIG. 14 perform A/D conversion of the Y signal and the c signal by utilizing the thus-generated re-sampling clocks as clocks. The Y signal and C signal thus A/D converted are written into an image memory 1515. Write addresses associated with the image memory 1515 are generated by an address generator 1517.
The CHSV reproducing apparatus shown in FIG. 14 repeats the aforesaid reproducing operation for all the four tracks (the first track to the fourth track) shown in FIGS. 6(a) and 6(b), thereby storing all the sampled values recorded in the four tracks on the magnetic disc 1501, in the image memory 1515 shown in FIG. 14.
Thereafter, an image processing circuit 1516 executes processes such as interpolation and rearrangement stored in the image memory 1515. The image processing circuit 1516 executes an LPF process for extracting a two-dimensional spatial frequency through a two-dimensional digital filter, thereby providing a low-band component Y.sub.L. The image processing circuit 1516 then performs arithmetic operations on (Y-YL) to provide the high frequency component YH of the sampled-value data of the Y signal. Accordingly, four kinds of data Y.sub.H, Y.sub.L, C.sub.R and C.sub.B are stored in the image memory 1515.
After the above process has been completed, the respective kinds of data are read from the image memory 1515 in predetermined order at a predetermined clock rate in accordance with the read addresses specified by the address generator 1517.
Of the Y.sub.H, Y.sub.L, C.sub.R and C.sub.B signals read from the image memory 1515, the Y.sub.L, C.sub.R and C.sub.B signals are converted into the R.sub.L, G.sub.L and B.sub.L signals by a matrix circuit 1519. The R.sub.L, G.sub.L and B.sub.L signals are added to the Y.sub.H signal by adders 1520, 1521 and 1522, respectively. The adders 1520, 1521 and 1522 output a (R.sub.L +Y.sub.H) signal, a (G.sub.L +Y.sub.H) signal and a (B.sub.L +Y.sub.H) signal.
The respective signals output from the adders 1520, 1521 and 1522 are converted into analog signals by corresponding D/A converters 1523, 1524 and 1525, so that the R, G and B signals are output.
As described above, the CHSV system proposed by the present applicant has the following features: It is capable of recording and reproducing a high-quality still image signal of the order of 1000 pixels.times.1000 pixels by using four tracks each of which conforms to the SV format and the magnetic disc recorded by the CHSV system can be reproduced even with a reproducing apparatus which conforms to the conventional SV format.
However, well-known ID signals, which are prescribed in the conventional SV format and which are recorded together with image signals on respective tracks, contain no information for use in discriminating between tracks recorded on the basis of the above CHSV system and tracks recorded on the basis of the conventional SV format. Accordingly, if a magnetic disc, recorded on the basis of the conventional SV format by an arbitrary recording apparatus, is reproduced with a reproducing apparatus based on the above CHSV format, various kinds of malfunction will take place; for example, different images may be overlapped on a display.
Accordingly, to realize a reproducing apparatus which conforms to the aforesaid CHSV system, it is necessary to prevent the aforementioned malfunction by determining whether tracks on a magnetic disc loaded in the apparatus are those recorded on the basis of the aforesaid CHSV format or those recorded on the basis of the conventional SV format.